[x265] [PATCH 181 of 307] x86: AVX512 interp_4tap_vert_ss_16xN
mythreyi at multicorewareinc.com
mythreyi at multicorewareinc.com
Sat Apr 7 04:32:59 CEST 2018
# HG changeset patch
# User Vignesh Vijayakumar<vignesh at multicorewareinc.com>
# Date 1511333868 -19800
# Wed Nov 22 12:27:48 2017 +0530
# Node ID ad1814e2ff60904208508512af07472dee380c51
# Parent 83f75ffc0773a2448efa7e6485cb009825edae41
x86: AVX512 interp_4tap_vert_ss_16xN
i444
Size | AVX2 performance | AVX512 performance
----------------------------------------------
16x4 | 13.31x | 32.24x
16x8 | 16.43x | 31.07x
16x12 | 17.26x | 30.29x
16x16 | 17.62x | 31.74x
16x32 | 16.66x | 35.61x
16x64 | 17.09x | 37.18x
diff -r 83f75ffc0773 -r ad1814e2ff60 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Nov 22 11:56:13 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Wed Nov 22 12:27:48 2017 +0530
@@ -4824,6 +4824,11 @@
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vpp = PFX(interp_4tap_vert_pp_32x24_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vpp = PFX(interp_4tap_vert_pp_32x32_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x4].filter_vss = PFX(interp_4tap_vert_ss_16x4_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x8].filter_vss = PFX(interp_4tap_vert_ss_16x8_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vss = PFX(interp_4tap_vert_ss_16x12_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vss = PFX(interp_4tap_vert_ss_16x16_avx512);
+ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vss = PFX(interp_4tap_vert_ss_16x32_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x8].filter_vss = PFX(interp_4tap_vert_ss_32x8_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vss = PFX(interp_4tap_vert_ss_32x16_avx512);
p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vss = PFX(interp_4tap_vert_ss_32x24_avx512);
@@ -4839,6 +4844,11 @@
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_vpp = PFX(interp_4tap_vert_pp_32x48_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_vpp = PFX(interp_4tap_vert_pp_32x64_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vss = PFX(interp_4tap_vert_ss_16x8_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x16].filter_vss = PFX(interp_4tap_vert_ss_16x16_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vss = PFX(interp_4tap_vert_ss_16x24_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x32].filter_vss = PFX(interp_4tap_vert_ss_16x32_avx512);
+ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vss = PFX(interp_4tap_vert_ss_16x64_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x16].filter_vss = PFX(interp_4tap_vert_ss_32x16_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_vss = PFX(interp_4tap_vert_ss_32x32_avx512);
p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_vss = PFX(interp_4tap_vert_ss_32x48_avx512);
@@ -4858,6 +4868,12 @@
p.chroma[X265_CSP_I444].pu[LUMA_64x32].filter_vpp = PFX(interp_4tap_vert_pp_64x32_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_64x16].filter_vpp = PFX(interp_4tap_vert_pp_64x16_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vss = PFX(interp_4tap_vert_ss_16x4_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x8].filter_vss = PFX(interp_4tap_vert_ss_16x8_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vss = PFX(interp_4tap_vert_ss_16x12_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x16].filter_vss = PFX(interp_4tap_vert_ss_16x16_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x32].filter_vss = PFX(interp_4tap_vert_ss_16x32_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vss = PFX(interp_4tap_vert_ss_16x64_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_32x8].filter_vss = PFX(interp_4tap_vert_ss_32x8_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_32x16].filter_vss = PFX(interp_4tap_vert_ss_32x16_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_32x24].filter_vss = PFX(interp_4tap_vert_ss_32x24_avx512);
diff -r 83f75ffc0773 -r ad1814e2ff60 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Wed Nov 22 11:56:13 2017 +0530
+++ b/source/common/x86/ipfilter8.asm Wed Nov 22 12:27:48 2017 +0530
@@ -11148,6 +11148,118 @@
;-------------------------------------------------------------------------------------------------------------
;avx512 chroma_vss code start
;-------------------------------------------------------------------------------------------------------------
+%macro PROCESS_CHROMA_VERT_SS_16x4_AVX512 0
+ movu ym1, [r0]
+ lea r6, [r0 + 2 * r1]
+ vinserti32x8 m1, [r6], 1
+ movu ym3, [r0 + r1]
+ vinserti32x8 m3, [r6 + r1], 1
+ punpcklwd m0, m1, m3
+ pmaddwd m0, m8
+ punpckhwd m1, m3
+ pmaddwd m1, m8
+
+ movu ym4, [r0 + 2 * r1]
+ vinserti32x8 m4, [r6 + 2 * r1], 1
+ punpcklwd m2, m3, m4
+ pmaddwd m2, m8
+ punpckhwd m3, m4
+ pmaddwd m3, m8
+
+ movu ym5, [r0 + r8]
+ vinserti32x8 m5, [r6 + r8], 1
+ punpcklwd m6, m4, m5
+ pmaddwd m6, m9
+ paddd m0, m6
+ punpckhwd m4, m5
+ pmaddwd m4, m9
+ paddd m1, m4
+
+ movu ym4, [r0 + 4 * r1]
+ vinserti32x8 m4, [r6 + 4 * r1], 1
+ punpcklwd m6, m5, m4
+ pmaddwd m6, m9
+ paddd m2, m6
+ punpckhwd m5, m4
+ pmaddwd m5, m9
+ paddd m3, m5
+
+ psrad m0, 6
+ psrad m1, 6
+ psrad m2, 6
+ psrad m3, 6
+ packssdw m0, m1
+ packssdw m2, m3
+
+ movu [r2], ym0
+ movu [r2 + r3], ym2
+ vextracti32x8 [r2 + 2 * r3], m0, 1
+ vextracti32x8 [r2 + r7], m2, 1
+%endmacro
+
+;-----------------------------------------------------------------------------------------------------------------
+; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx)
+;-----------------------------------------------------------------------------------------------------------------
+%if ARCH_X86_64
+INIT_ZMM avx512
+cglobal interp_4tap_vert_ss_16x4, 5, 9, 10
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, r1
+ shl r4d, 7
+%ifdef PIC
+ lea r5, [pw_ChromaCoeffVer_32_avx512]
+ mova m8, [r5 + r4]
+ mova m9, [r5 + r4 + mmsize]
+%else
+ lea r5, [pw_ChromaCoeffVer_32_avx512 + r4]
+ mova m8, [r5]
+ mova m9, [r5 + mmsize]
+%endif
+
+ lea r7, [3 * r3]
+ lea r8, [3 * r1]
+ PROCESS_CHROMA_VERT_SS_16x4_AVX512
+ RET
+%endif
+
+%macro FILTER_VER_SS_CHROMA_16xN_AVX512 1
+INIT_ZMM avx512
+cglobal interp_4tap_vert_ss_16x%1, 5, 9, 10
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, r1
+ shl r4d, 7
+%ifdef PIC
+ lea r5, [pw_ChromaCoeffVer_32_avx512]
+ mova m8, [r5 + r4]
+ mova m9, [r5 + r4 + mmsize]
+%else
+ lea r5, [pw_ChromaCoeffVer_32_avx512 + r4]
+ mova m8, [r5]
+ mova m9, [r5 + mmsize]
+%endif
+
+ lea r7, [3 * r3]
+ lea r8, [3 * r1]
+%rep %1/4 - 1
+ PROCESS_CHROMA_VERT_SS_16x4_AVX512
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+%endrep
+ PROCESS_CHROMA_VERT_SS_16x4_AVX512
+ RET
+%endmacro
+
+%if ARCH_X86_64
+ FILTER_VER_SS_CHROMA_16xN_AVX512 8
+ FILTER_VER_SS_CHROMA_16xN_AVX512 12
+ FILTER_VER_SS_CHROMA_16xN_AVX512 16
+ FILTER_VER_SS_CHROMA_16xN_AVX512 24
+ FILTER_VER_SS_CHROMA_16xN_AVX512 32
+ FILTER_VER_SS_CHROMA_16xN_AVX512 64
+%endif
+
%macro PROCESS_CHROMA_VERT_SS_32x4_AVX512 0
movu m1, [r0]
lea r6, [r0 + 2 * r1]
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