[x265] [PATCH 182 of 307] x86: AVX512 interp_4tap_vert_ss_48x64
mythreyi at multicorewareinc.com
mythreyi at multicorewareinc.com
Sat Apr 7 04:33:00 CEST 2018
# HG changeset patch
# User Vignesh Vijayakumar<vignesh at multicorewareinc.com>
# Date 1511337892 -19800
# Wed Nov 22 13:34:52 2017 +0530
# Node ID 3d6605772d179c329fffc669cbecc64afd8c8dff
# Parent ad1814e2ff60904208508512af07472dee380c51
x86: AVX512 interp_4tap_vert_ss_48x64
AVX2 performance : 16.34x
AVX512 performance : 35.69x
diff -r ad1814e2ff60 -r 3d6605772d17 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Nov 22 12:27:48 2017 +0530
+++ b/source/common/x86/asm-primitives.cpp Wed Nov 22 13:34:52 2017 +0530
@@ -4883,6 +4883,7 @@
p.chroma[X265_CSP_I444].pu[LUMA_64x48].filter_vss = PFX(interp_4tap_vert_ss_64x48_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_64x32].filter_vss = PFX(interp_4tap_vert_ss_64x32_avx512);
p.chroma[X265_CSP_I444].pu[LUMA_64x16].filter_vss = PFX(interp_4tap_vert_ss_64x16_avx512);
+ p.chroma[X265_CSP_I444].pu[LUMA_48x64].filter_vss = PFX(interp_4tap_vert_ss_48x64_avx512);
p.cu[BLOCK_8x8].dct = PFX(dct8_avx512);
p.cu[BLOCK_8x8].idct = PFX(idct8_avx512);
diff -r ad1814e2ff60 -r 3d6605772d17 source/common/x86/ipfilter8.asm
--- a/source/common/x86/ipfilter8.asm Wed Nov 22 12:27:48 2017 +0530
+++ b/source/common/x86/ipfilter8.asm Wed Nov 22 13:34:52 2017 +0530
@@ -11373,6 +11373,155 @@
FILTER_VER_SS_CHROMA_32xN_AVX512 64
%endif
+%macro PROCESS_CHROMA_VERT_SS_48x4_AVX512 0
+ movu m1, [r0]
+ lea r6, [r0 + 2 * r1]
+ movu m10, [r6]
+ movu m3, [r0 + r1]
+ movu m12, [r6 + r1]
+ punpcklwd m0, m1, m3
+ punpcklwd m9, m10, m12
+ pmaddwd m0, m16
+ pmaddwd m9, m16
+ punpckhwd m1, m3
+ punpckhwd m10, m12
+ pmaddwd m1, m16
+ pmaddwd m10, m16
+
+ movu m4, [r0 + 2 * r1]
+ movu m13, [r6 + 2 * r1]
+ punpcklwd m2, m3, m4
+ punpcklwd m11, m12, m13
+ pmaddwd m2, m16
+ pmaddwd m11, m16
+ punpckhwd m3, m4
+ punpckhwd m12, m13
+ pmaddwd m3, m16
+ pmaddwd m12, m16
+
+ movu m5, [r0 + r7]
+ movu m14, [r6 + r7]
+ punpcklwd m6, m4, m5
+ punpcklwd m15, m13, m14
+ pmaddwd m6, m17
+ pmaddwd m15, m17
+ paddd m0, m6
+ paddd m9, m15
+ punpckhwd m4, m5
+ punpckhwd m13, m14
+ pmaddwd m4, m17
+ pmaddwd m13, m17
+ paddd m1, m4
+ paddd m10, m13
+
+ movu m4, [r0 + 4 * r1]
+ movu m13, [r6 + 4 * r1]
+ punpcklwd m6, m5, m4
+ punpcklwd m15, m14, m13
+ pmaddwd m6, m17
+ pmaddwd m15, m17
+ paddd m2, m6
+ paddd m11, m15
+ punpckhwd m5, m4
+ punpckhwd m14, m13
+ pmaddwd m5, m17
+ pmaddwd m14, m17
+ paddd m3, m5
+ paddd m12, m14
+
+ psrad m0, 6
+ psrad m1, 6
+ psrad m2, 6
+ psrad m3, 6
+ psrad m9, 6
+ psrad m10, 6
+ psrad m11, 6
+ psrad m12, 6
+ packssdw m0, m1
+ packssdw m2, m3
+ packssdw m9, m10
+ packssdw m11, m12
+
+ movu [r2], m0
+ movu [r2 + r3], m2
+ movu [r2 + 2 * r3], m9
+ movu [r2 + r8], m11
+
+ movu ym1, [r0 + mmsize]
+ vinserti32x8 m1, [r6 + mmsize], 1
+ movu ym3, [r0 + r1 + mmsize]
+ vinserti32x8 m3, [r6 + r1 + mmsize], 1
+ punpcklwd m0, m1, m3
+ pmaddwd m0, m16
+ punpckhwd m1, m3
+ pmaddwd m1, m16
+
+ movu ym4, [r0 + 2 * r1 + mmsize]
+ vinserti32x8 m4, [r6 + 2 * r1 + mmsize], 1
+ punpcklwd m2, m3, m4
+ pmaddwd m2, m16
+ punpckhwd m3, m4
+ pmaddwd m3, m16
+
+ movu ym5, [r0 + r7 + mmsize]
+ vinserti32x8 m5, [r6 + r7 + mmsize], 1
+ punpcklwd m6, m4, m5
+ pmaddwd m6, m17
+ paddd m0, m6
+ punpckhwd m4, m5
+ pmaddwd m4, m17
+ paddd m1, m4
+
+ movu ym4, [r0 + 4 * r1 + mmsize]
+ vinserti32x8 m4, [r6 + 4 * r1 + mmsize], 1
+ punpcklwd m6, m5, m4
+ pmaddwd m6, m17
+ paddd m2, m6
+ punpckhwd m5, m4
+ pmaddwd m5, m17
+ paddd m3, m5
+
+ psrad m0, 6
+ psrad m1, 6
+ psrad m2, 6
+ psrad m3, 6
+ packssdw m0, m1
+ packssdw m2, m3
+
+ movu [r2 + mmsize], ym0
+ movu [r2 + r3 + mmsize], ym2
+ vextracti32x8 [r2 + 2 * r3 + mmsize], m0, 1
+ vextracti32x8 [r2 + r8 + mmsize], m2, 1
+%endmacro
+
+%if ARCH_X86_64
+INIT_ZMM avx512
+cglobal interp_4tap_vert_ss_48x64, 5, 9, 18
+ add r1d, r1d
+ add r3d, r3d
+ sub r0, r1
+ shl r4d, 7
+%ifdef PIC
+ lea r5, [pw_ChromaCoeffVer_32_avx512]
+ mova m16, [r5 + r4]
+ mova m17, [r5 + r4 + mmsize]
+%else
+ lea r5, [pw_ChromaCoeffVer_32_avx512 + r4]
+ mova m16, [r5]
+ mova m17, [r5 + mmsize]
+%endif
+ lea r7, [3 * r1]
+ lea r8, [3 * r3]
+
+%rep 15
+ PROCESS_CHROMA_VERT_SS_48x4_AVX512
+ lea r0, [r0 + 4 * r1]
+ lea r2, [r2 + 4 * r3]
+%endrep
+ PROCESS_CHROMA_VERT_SS_48x4_AVX512
+ RET
+%endif
+
%macro PROCESS_CHROMA_VERT_SS_64x2_AVX512 0
movu m1, [r0]
movu m3, [r0 + r1]
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