[x265] [PATCH] asm: code for pixel_sse_sp_4xN

[murugan at multicorewareinc.com]

# HG changeset patch
# User Murugan Vairavel <murugan at multicorewareinc.com>
# Date 1385644665 -19800
#      Thu Nov 28 18:47:45 2013 +0530
# Node ID d085a3b535c8587bb9ce8a0adcc26fe47b166394
# Parent  949f85337789c8d00f39ed1a010990efe67ebcf4
asm: code for pixel_sse_sp_4xN

diff -r 949f85337789 -r d085a3b535c8 source/common/x86/pixel-a.asm
--- a/source/common/x86/pixel-a.asm	Wed Nov 27 18:10:14 2013 -0600
+++ b/source/common/x86/pixel-a.asm	Thu Nov 28 18:47:45 2013 +0530
@@ -1400,6 +1400,81 @@
 ; int pixel_ssd_sp ( int16_t *, intptr_t, uint8_t *, intptr_t )
 ;-----------------------------------------------------------------------------
 
+cglobal pixel_ssd_sp_4x4_internal
+    movh          m0,    [r0]
+    movh          m1,    [r0 + r1]
+    punpcklqdq    m0,    m1
+    movd          m2,    [r2]
+    movd          m3,    [r2 + r3]
+    punpckldq     m2,    m3
+    pmovzxbw      m2,    m2
+    psubw         m0,    m2
+    movh          m4,    [r0 + 2 * r1]
+    movh          m5,    [r0 + r4]
+    punpcklqdq    m4,    m5
+    movd          m6,    [r2 + 2 * r3]
+    lea           r2,    [r2 + 2 * r3]
+    movd          m1,    [r2 + r3]
+    punpckldq     m6,    m1
+    pmovzxbw      m6,    m6
+    psubw         m4,    m6
+    pmaddwd       m0,    m0
+    pmaddwd       m4,    m4
+    paddd         m0,    m4
+    paddd         m7,    m0
+    ret
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_4x4( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_4x4, 4, 5, 8, src1, stride1, src2, stride2
+    pxor     m7,     m7
+    add      r1,     r1
+    lea      r4,     [r1 * 3]
+    call     pixel_ssd_sp_4x4_internal
+    HADDD    m7,     m1
+    movd     eax,    m7
+    RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_4x8( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_4x8, 4, 5, 8, src1, stride1, src2, stride2
+    pxor     m7,     m7
+    add      r1,     r1
+    lea      r4,     [r1 * 3]
+    call     pixel_ssd_sp_4x4_internal
+    lea      r0,     [r0 + 4 * r1]
+    lea      r2,     [r2 + 2 * r3]
+    call     pixel_ssd_sp_4x4_internal
+    HADDD    m7,     m1
+    movd     eax,    m7
+    RET
+
+;-----------------------------------------------------------------------------
+; int pixel_ssd_sp_4x16( int16_t *, intptr_t, uint8_t *, intptr_t )
+;-----------------------------------------------------------------------------
+INIT_XMM sse4
+cglobal pixel_ssd_sp_4x16, 4, 5, 8, src1, stride1, src2, stride2
+    pxor     m7,     m7
+    add      r1,     r1
+    lea      r4,     [r1 * 3]
+    call     pixel_ssd_sp_4x4_internal
+    lea      r0,     [r0 + 4 * r1]
+    lea      r2,     [r2 + 2 * r3]
+    call     pixel_ssd_sp_4x4_internal
+    lea      r0,     [r0 + 4 * r1]
+    lea      r2,     [r2 + 2 * r3]
+    call     pixel_ssd_sp_4x4_internal
+    lea      r0,     [r0 + 4 * r1]
+    lea      r2,     [r2 + 2 * r3]
+    call     pixel_ssd_sp_4x4_internal
+    HADDD    m7,     m1
+    movd     eax,    m7
+    RET
+
 cglobal pixel_ssd_sp_8x4_internal
     movu         m0,    [r0]
     movu         m1,    [r0 + r1]