[x265] [PATCH 03 of 11] asm: intra_pred_ang4_33 improved by ~44% over SSE4
praveen at multicorewareinc.com
praveen at multicorewareinc.com
Thu Apr 2 12:49:37 CEST 2015
# HG changeset patch
# User Praveen Tiwari <praveen at multicorewareinc.com>
# Date 1427953090 -19800
# Thu Apr 02 11:08:10 2015 +0530
# Node ID ac65d39da56579d6b45ac09c0ed7a55af4ff1856
# Parent 46a501f29b887264074341b1432135e5539d27c5
asm: intra_pred_ang4_33 improved by ~44% over SSE4
AVX2:
intra_ang_4x4[33] 8.42x 94.09 792.57
SSE4:
intra_ang_4x4[33] 4.71x 167.48 788.59
diff -r 46a501f29b88 -r ac65d39da565 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Thu Apr 02 10:47:20 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Thu Apr 02 11:08:10 2015 +0530
@@ -1612,6 +1612,7 @@
p.cu[BLOCK_4x4].intra_pred[30] = x265_intra_pred_ang4_30_avx2;
p.cu[BLOCK_4x4].intra_pred[31] = x265_intra_pred_ang4_31_avx2;
p.cu[BLOCK_4x4].intra_pred[32] = x265_intra_pred_ang4_32_avx2;
+ p.cu[BLOCK_4x4].intra_pred[33] = x265_intra_pred_ang4_33_avx2;
p.cu[BLOCK_8x8].intra_pred[3] = x265_intra_pred_ang8_3_avx2;
p.cu[BLOCK_8x8].intra_pred[33] = x265_intra_pred_ang8_33_avx2;
p.cu[BLOCK_8x8].intra_pred[4] = x265_intra_pred_ang8_4_avx2;
diff -r 46a501f29b88 -r ac65d39da565 source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h Thu Apr 02 10:47:20 2015 +0530
+++ b/source/common/x86/intrapred.h Thu Apr 02 11:08:10 2015 +0530
@@ -180,6 +180,7 @@
void x265_intra_pred_ang4_30_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang4_31_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang4_32_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang4_33_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang8_3_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang8_33_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang8_4_avx2(pixel* dst, intptr_t dstStride, const pixel* srcPix, int dirMode, int bFilter);
diff -r 46a501f29b88 -r ac65d39da565 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm Thu Apr 02 10:47:20 2015 +0530
+++ b/source/common/x86/intrapred8.asm Thu Apr 02 11:08:10 2015 +0530
@@ -515,6 +515,7 @@
intra_pred4_shuff1: db 0, 1, 1, 2, 2, 3, 3, 4, 0, 1, 1, 2, 2, 3, 3, 4, 0, 1, 1, 2, 2, 3, 3, 4, 1, 2, 2, 3, 3, 4, 4, 5
intra_pred4_shuff2: db 0, 1, 1, 2, 2, 3, 3, 4, 0, 1, 1, 2, 2, 3, 3, 4, 1, 2, 2, 3, 3, 4, 4, 5, 1, 2, 2, 3, 3, 4, 4, 5
intra_pred4_shuff31: db 0, 1, 1, 2, 2, 3, 3, 4, 1, 2, 2, 3, 3, 4, 4, 5, 1, 2, 2, 3, 3, 4, 4, 5, 2, 3, 3, 4, 4, 5, 5, 6
+intra_pred4_shuff33: db 0, 1, 1, 2, 2, 3, 3, 4, 1, 2, 2, 3, 3, 4, 4, 5, 2, 3, 3, 4, 4, 5, 5, 6, 3, 4, 4, 5, 5, 6, 6, 7
c_ang4_mode_27: db 30, 2, 30, 2, 30, 2, 30, 2, 28, 4, 28, 4, 28, 4, 28, 4, 26, 6, 26, 6, 26, 6, 26, 6, 24, 8, 24, 8, 24, 8, 24, 8
c_ang4_mode_28: db 27, 5, 27, 5, 27, 5, 27, 5, 22, 10, 22, 10, 22, 10, 22, 10, 17, 15, 17, 15, 17, 15, 17, 15, 12, 20, 12, 20, 12, 20, 12, 20
@@ -522,6 +523,7 @@
c_ang4_mode_30: db 19, 13, 19, 13, 19, 13, 19, 13, 6, 26, 6, 26, 6, 26, 6, 26, 25, 7, 25, 7, 25, 7, 25, 7, 12, 20, 12, 20, 12, 20, 12, 20
c_ang4_mode_31: db 15, 17, 15, 17, 15, 17, 15, 17, 30, 2, 30, 2, 30, 2, 30, 2, 13, 19, 13, 19, 13, 19, 13, 19, 28, 4, 28, 4, 28, 4, 28, 4
c_ang4_mode_32: db 11, 21, 11, 21, 11, 21, 11, 21, 22, 10, 22, 10, 22, 10, 22, 10, 1, 31, 1, 31, 1, 31, 1, 31, 12, 20, 12, 20, 12, 20, 12, 20
+c_ang4_mode_33: db 6, 26, 6, 26, 6, 26, 6, 26, 12, 20, 12, 20, 12, 20, 12, 20, 18, 14, 18, 14, 18, 14, 18, 14, 24, 8, 24, 8, 24, 8, 24, 8
ALIGN 32
;; (blkSize - 1 - x)
@@ -15578,3 +15580,19 @@
movd [r0], xm0
pextrd [r0 + r1], xm0, 1
RET
+
+INIT_YMM avx2
+cglobal intra_pred_ang4_33, 3, 3, 1
+ vbroadcasti128 m0, [r2 + 1]
+ pshufb m0, [intra_pred4_shuff33]
+ pmaddubsw m0, [c_ang4_mode_33]
+ pmulhrsw m0, [pw_1024]
+ packuswb m0, m0
+
+ movd [r0], xm0
+ pextrd [r0 + r1], xm0, 1
+ vextracti128 xm0, m0, 1
+ lea r0, [r0 + 2 * r1]
+ movd [r0], xm0
+ pextrd [r0 + r1], xm0, 1
+ RET
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